PCIe Root Complexes still expose PCI-compatible configuration mechanisms. Operating systems use the same driver model for PCI and PCIe devices. 9. Practical Example: Programming a PCI Controller To access a PCI device’s configuration space on x86:
// Write to CONFIG_ADDRESS (I/O port 0xCF8) uint32_t addr = (1 << 31) // Enable bit | (bus << 16) | (dev << 11) | (func << 8) | (offset & 0xFC); // Dword-aligned outl(0xCF8, addr); // Read from CONFIG_DATA (I/O port 0xCFC) uint32_t data = inl(0xCFC); pci controller
| Feature | Legacy PCI Controller | PCIe Root Complex | | :--- | :--- | :--- | | Topology | Shared parallel bus | Point-to-point serial lanes (x1, x4, x8, x16) | | Bandwidth (per lane) | 133 MB/s (max) | 2 GB/s per direction (PCIe 6.0) | | Configuration Space | Same 256-byte header | Extended to 4KB (PCIe capability structures) | | Enumeration | Type 0/1 cycles | Same, but forwarded as Transaction Layer Packets (TLPs) | | Interrupts | Legacy INTx lines | MSI/MSI-X (Message Signaled Interrupts) | Practical Example: Programming a PCI Controller To access